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If you’re interested in a career in reconfigurable HW/SW solutions, Flex Logix is right for you.

You can learn more and have more opportunities for growth at an innovative startup company like Flex Logix which is the leader in reconfigurable computing SW/HW solutions.

We have more than 60 patents and applications for inventions that give us a fundamental competitive advantage in programmable interconnects and reconfigurable tensor computing for AI and DSP.

Our technology is already working in >20 chips at dozens of customers and our market adoption is growing rapidly. Work with some of the biggest systems and chip companies in the world and some of the smartest SW/HW developers on our team.

You can work for us either in our Austin TX office or our Mountain View CA office.

How to Apply

Only apply if you are highly qualified, very smart, super-motivated, willing to work hard and are interested, challenged and motivated by the kind of technology we develop.

Tell us which job you are interested in and send us your resume or linked-in page link using the attached form and the hiring manager will get back to you promptly.

Principal Verification Engineer

Senior Engineer/Principal

Responsibilities

Candidate will be involved in functional verification of embedded FPGA cores as well as DSP and Inference AI IP.

Responsible for all aspects of verification including:

  • Serve as a verification leader for the organization

  • Possibly manage 1 or 2 verification engineers

  • Development of verification testbenches using SystemVerilog/UVM

  • Development of test plans and execution to plan and coverage goals

  • Development of coverage plans and metrics, drive coverage activities and test writing

  • Automation of the verification process

  • Gate-Level simulation and debug

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Required Experience

  • BSEE/MSEE with at least 10+ years of relevant experience.
  • Expert in Verilog and SystemVerilog testbench design, stimulus, and debug
  • Proven ability to craft requirements and design specifications into test planor verification plan documentation and execute to plan and coverage goals
  • Strong scripting language skills such as Perl, Python, and csh for thepurposes of automation and management of large parallel simulation tasks
  • Hands-on experience with standard functional simulators like Questa,NCSIM or VCS
  • Experience running and debugging gate simulations
  • Excellent planning and progress tracking skills
  • Good written, in-person and remote communication skills

Desired skills:

  • Experience with DFT pattern verification and debug
  • Experience implementing formal verification flows
  • FPGA verification experience
  • Familiarity with continuous integration infrastructure such as Jenkins
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DFT Architect

Senior Engineer/Principal

Responsibilities

DFT architect will work closely with the design team, embedded FPGA technologists, customers and physical designers to define appropriate DFT features, structures, and methodologies for our products. You will also work with business and operations leaders to define appropriate test coverage targets that meet quality and business needs.

Primary Responsibilities:

  • Architect DFT solutions catered to eFPGA, DSP, and AI Inference IP
  • Develop DFT flows for high-quality production
  • Implement and verify DFT solutions
  • Lead other team members to successfully implement and verify DFT solutions
  • Automate the all DFT processes and flows
  • Interface with customers as issues arise or to clarify solutions
  • Interface with DFT EDA vendors
  • Interface with contractors or partners
  • Clearly communicate and document methods and scripts
  • Clearly communicate status throughout the project
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Required Experience

  • Extensive experience in leading DFT for high-quality products that reached high-volume production
  • Proven experience in defining strategy and implementation of at least 1 high-volume production SOC
  • Proven experience setting-up flows with standard EDA tools
  • Experience verifying solutions
  • Deep understanding of how leading DFT industry tools work
  • Deep understanding of defect density and the implication of DFT methods on physical design
  • Recent hands-on experience implementing DFT on a significant SOC
  • BSEE/MSEE with 5 or more years of relevant industry experience
  • Must be innovative and be able to cater solutions to particular designs
  • Must have hands-on experience in scripting languages
  • Must have hands-on experience in testbench creation and gate-level simulations with SDF

Preferred experience OR willing to quickly learn:

  • Understanding of computer architectures for DSP and AI
  • DFT needs and solutions for automotive
  • Understanding of FPGA architectures and how to best test them
  • Running logic synthesis and static timing tools

Must be passionate about being part of an aggressive, venture-backed startup team that is changing computation for the future (more secure, higher performance per watt). Must be entrepreneurial, innovative problem solver and willing to work hard.

Must live in Silicon Valley or Austin area and have US citizenship or permanent residency (“green card”), or holding a current H1-B visa

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