Careers
You can learn more and have more opportunities for growth at an innovative startup company like Flex Logix which is the leader in reconfigurable computing SW/HW solutions.
We have more than 60 patents and applications for inventions that give us a fundamental competitive advantage in programmable interconnects and reconfigurable tensor computing for AI and DSP.
Our technology is already working in >20 chips at dozens of customers and our market adoption is growing rapidly. Work with some of the biggest systems and chip companies in the world and some of the smartest SW/HW developers on our team.
You can work for us either in our Austin TX office or our Mountain View CA office.
How to Apply
Only apply if you are highly qualified, very smart, super-motivated, willing to work hard and are interested, challenged and motivated by the kind of technology we develop.
Tell us which job you are interested in and send us your resume or linked-in page link using the attached form and the hiring manager will get back to you promptly.
Responsibilities
- Generate block level static timing constraints and run STA
- Build IP floor-plan including pin placement, partitions and power grid.
- Develop and validate high performance low power clock network guidelines.
- Perform block level place and route and close the design to meet timing, area and power constraints.
- Generate and Implement ECOs to fix timing, noise and EM IR violations.
- Run Physical design verification flow at block level and provide guidelines to fix LVS/DRC violations to other designers.
- Participate in establishing CAD and physical design methodologies for correct construction designs.
Required Experience
- Bachelors or Master’s Degree in EE/CS required.
- 7+ years of Physical Design experience on IP and/or SOC designs.
- Experience in developing and implementing Power-grid and Clock specifications.
- Deep knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, floor-planning, and place & route.
- Deep understanding of scripting languages such as Perl/Tcl,
- Basic understanding of Extraction and STA methodology and tools.
- Deep understanding of Physical Design Verification methodology to debug LVS/DRC issues at block level.
- Strong understanding of all aspects of Physical construction, Integration and Physical Verification.
- Knowledge of Basic HDL languages like Verilog to be able to work with logic design teams for timing fixes.
