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Reconfigurable computing

so your SoC can adapt

Reconfigurable computing gives you the best combination of the performance of hard-wired with programmability so you can adapt to new needs, protocols, standards, and algorithms.

eFPGA IP is proven in more than 25 chips with many more in design. DSP/AI IP now available: world class performance at a fraction of the cost and power.

#1 in embedded FPGA (eFPGA)

>20 customers with >25 working chips and many more in design.

Best PPA (power/performance/area) in a dozen nodes from 180nm to 18A.

Super fast or super low power.

1K to >1M LUTs with DSP and BRAM options.

Proven EFLX Compiler software.

Integrate your existing FPGA into your SoC/MPU

Integrate flexible parallel processing performance in your SoC or MPU. Keep the flexibility and programmability of your FPGA while cutting power and cost 5-10x. Double compute density (two chips into one).

Micro FPGA

Renesas is using TSMC 40nm 1K LUTs to build a family of FPGAs unlike any before:

<50¢ in volume, tiny, milliwatts for very high-volume applications.

Based on Flex Logix EFLX eFPGA and Compiler.

Embed Fast Flexibility in MCUs and SoCs

eFPGA can enable you or your customers to use the parallelism of eFPGA to run workloads like compression faster than the processor.

And eFPGA can enable GPIO to be programmable to interface with ANY customer chip.

Growing Ecosystem and Partners

Many ASIC/Design Services firms have already done one or more tape-out with eFPGA.

Many RTL IP companies have FPGA-compatible RTL you can use on your eFPGA for encryption, compression, etc.

Two front-end tools are proven for Verilog Synthesis front ends to the EFLX Compiler.

InferX gives your SoC World Class DSP or AI Performance

InferX is 80% hard-wired and 100% reconfigurable, so it is both super efficient and adaptable. We program it to run DSP or AI.

You can have performance as good or better than the best DSP-FPGA or AI-GPU in your SoC at a fraction of the cost and power.

60 US Patents and Applications

FPGA interconnect with 1/2 transistors and 1/2 metal layers.

Self-connecting compute tiles arrayable for scalable capacity and compute.

Rapidly reconfigurable, eFPGA-controlled tensor processors.

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