Reconfigurable computing gives you the best combination of the performance of hard-wired with programmability so you can adapt to new needs, protocols, standards, and algorithms.
eFPGA proven in dozens of chips. AI/DSP IP in Q2 2023.
Embed flexible parallel processing performance in your SoC.
As fast as 500MHz over worst-case conditions. Or super low power.
1K to >1M LUTs with DSP and BRAM options.
>20 working chips and dozens more in design.
Proven graphical user interface compiler and design/debug tools.
Integrate flexible parallel processing performance in your FinFet SoC.
Keep the flexibility and programmability of your FPGA while cutting power and cost 5-10x.
Double compute density (two chips into one).
Renesas is using TSMC 40nm 1K LUTs to build a family of FPGAs unlike any before:
<50¢ in volume, tiny, milliwatts for very high-volume applications.
Based on Flex Logix EFLX eFPGA and Compiler.
eFPGA can enable you or your customers to use the parallelism of eFPGA to run workloads like compression faster than the processor.
And eFPGA can enable GPIO to be programmable to interface with ANY customer chip.
For maximum performance at minimum area, use programmable eFPGA to control a hardwired data path. In Flex Logix’ AI Compute tile we hardwire the MACs into Tensor Processors that are much smaller and faster than what’s possible in FPGA. Our RTL can run >500MHz in 16nm and 800MHz in 7nm and is reconfigurable in μseconds.
Many ASIC/Design Services firms have already done one or more tape-out with eFPGA.
Many RTL IP companies have FPGA-compatible RTL you can use on your eFPGA for encryption, compression, etc.
Two front-end tools are proven for Verilog Synthesis front ends to the EFLX Compiler.
FPGA interconnect with 1/2 transistors and 1/2 metal layers.
Self-connecting compute tiles arrayable for scalable capacity and compute.
Rapidly reconfigurable, eFPGA-controlled tensor processors.
