EFLX Compiler Software Evaluation
We provide a free license for your team to evaluate our EFLX Compiler tool suite to assess the GUI interface and tools, and to run your RTL on the process node you are interested in to determine performance and area.
Contact us here to arrange for your software evaluation with our team.
Our compiler comes integrated with your choice of Synopsys Synplify or Yosys.
Or our compiler can work with your copy of Synplify.
Most customers prefer Synplify because it works better on large designs and generally delivers better results.
But some customers prefer Yosys for smaller designs and because it can be used without a license server (especially for our customers who distribute our tools to their customers).
The EFLX Compiler has been in use by dozens of customers for many years from 180nm to 7nm and on over 20 silicon-proven chips.
The EFLX Compiler does placement, routing, timing generation, and bitstream file generation. You can use it with Tcl scripting APIs or our advanced GUI interface.
Timing constraints are specified using Synopsys Design Constraints (SDC). Timing can be analyzed at any step in the place and route flow to help optimize critical paths. Timing can be viewed in multiple process corners.
Integrate our SW in your tool chain
Enable Your Customers to Program Your SoC
Many of our customers want to enable their customers to program the eFPGA in the SoC.
We are doing this now with Renesas’ ForgeFPGA for example where their GUI interface is built on top of our EFLX Compiler using Yosys for synthesis.
We can enable you in the same way with Yosys or Synplify.
Partionable FPGA allows you to give them libraries of subroutines that are pre-compiled so it’s easier for them to program. Or you can give them some modules like UARTs/SPIs and let them program other blocks without your code and theirs interacting.