Inventions
Flex Logix Patents
US PATENT 9,240,791
Clock Distribution Architecture for Logic Tiles of an Integrated Circuit and Method of Operation Thereof
US PATENT 9,496,876
Clock Distribution Architecture for Logic Tiles of an Integrated Circuit and Method of Operation Thereof
US PATENT 9,503,092
Mixed-Radix and/or Mixed-Mode Switch Matrix Architecture and Integrated Circuit, and Method of Operating Same
US PATENT 9,543,958
Multiplexer-Memory Cell Circuit, Layout Thereof and Method Manufacturing Same
US PATENT 9,755,651
Multiplexer-Memory Cell Circuit, Layout Thereof and Method of Manufacturing Same
US PATENT 9,786,361
Programmable Decoupling Capacitance of Configurable Logic Circuitry and Method of Operating Same
US PATENT 9,793,898
Mixed-Radix and/or Mixed-Mode Switch Matrix Architecture and Integrated Circuit, and Method of Operating Same
US PATENT 9,817,933
Network Architectures for Boundary-less Hierarchical Interconnects (this is a patent with inventors Cheng Wang and Dejan Markovic based on their work while at UCLA, before Flex Logix; Flex Logix is the exclusive licensee)
US PATENT 9,882,568
Clock Distribution Architecture for Logic Tiles of an Integrated Circuit and Method of Operation Thereof
US PATENT 9,906,225
Integrated Circuit Including an Array of Logic Tiles, Each Logic Tile Including a Configurable Interconnect Network.
US PATENT 9,923,555
Fine-grained Power Gating in FPGA Interconnects. (this is a patent with inventors Cheng Wang and Dejan Markovic based on their work while at UCLA, before Flex Logix; Flex Logix is the exclusive licensee)
US PATENT 9,941,887
Multiplexer-memory Cell Circuit, Layout Thereof and Method of Manufacturing Same
US PATENT 9,973,194
Block Memory Layout and Architecture for Programmable Logic IC, and Method of Operating Same
US PATENT 10,176,865
Programmable Decoupling Capacitance of Configurable Logic Circuitry and Method of Operating Same
US PATENT 10,250,262
Integrated Circuit Including an Array of Logic Tiles, Each Logic Tile Including a Configurable Switch Interconnect Network
US PATENT 10,348,307
Clock Distribution and Generation Architecture for Logic Tiles of an Integrated Circuit and Method of Operating Same
US PATENT 10,348,308
Clock Architecture, including Clock Mesh Fabric, for FPGA, and Method of Operating Same
US PATENT 10,411,711
FPGA having a virtual array of logic tiles, and method of configuring and operating same
US PATENT 10,411,712
FPGA having programmable powered-up/powered-down logic tiles, and method of configuring and operating same
US PATENT 10,523,209
Test Circuitry and Techniques for Logic Tiles of FPGA
US PATENT 10,587,269
Integrated Circuit including an array of logic tiles, each logic tile including a configurable switch interconnect network
US PATENT 10,587,271
Clock distribution and generation architecture for logic tiles of an integrated circuit and method of operating same
US PATENT 10,680,616
Block Memory Layout and Architecture for Programmable Logic IC, and Method of Operating the same
US PATENT 10,684,975
One-Hot-Bit Multiplexer Control Circuitry and Technique
US PATENT 10,686,447
Modular Field Programmable Gate Array, and Method of Configuring and Operating Same
US PATENT 10,686,448
Clock Architecture Including Clock Mesh Fabric for FPGA, and Method of Operating Same
US PATENT 10,693,469
Multiplier-Accumulator Circuit, Logic Tile Architecture for Multiply-Accumulate, and IC including Logic Tile Array
US PATENT 10,775,433
Programmable/Configurable Logic Circuitry, Control Circuitry and Method of Dynamic Context Switching
US PATENT 10,778,228
Reconfigurable Data Processing Pipeline, and Method of Operating Same
US PATENT 10,855,284
Process of routing tile-to-tile interconnects of an FPGA, and method of manufacturing an FPGA
US PATENT 10,867,096
FPGA implementing partial data path processing
US PATENT 10,886,922
Test circuitry and techniques for logic tiles of FPGA
US PATENT 10,972,103
Multiplier-Accumulator Circuitry, and Processing Pipeline Including Same
US PATENT 11,194, 585
Winograd
US PATENT 11,288,076
MAC Load/Store Chain
