See us at DAC June 24-26 and TSMC Japan June 28


eXpreso™ EFLX Compiler

eXpreso is our powerful 2nd generation EFLX eFPGA Compiler in evaluation now by alpha customers and in production later this year.
It replaces our original EFLX Compiler that has been used by hundreds of customers to successfully build dozens of chips for almost 10 years.
eXpreso delivers up to 1.5x higher Max, up to 2x packing density increase, and up to 10x faster compile time.
eXpreso uses Synopsys Synplify for powerful, efficient synthesis then does placement, routing, timing generation and bit file generation. 
The place and route algorithms have been rewritten to take full advantage of our proprietary XFLX and ArrayLinx interconnects enabling utilization of up to 100% of the LUTs.  Shown to the left is a Xiphera cryptography algorithm with 98.6% LUT utilization. This is better utilization than any other FPGA architecture by a significant amount.
Timing constraints are specified using Synopsys Design Contraints (SDC). Timing can be analyzed at any step in the place route flow to help optimize critical paths.  Timing is generated for all process corners using the foundry standard cells.
eXpreso is still in development with GUI improvements, Flow/Project Manager and eLA logic analyzer coming soon.


Synthesis Options

Our compiler comes integrated with your choice of Synopsys Synplify or Yosys.

Or our compiler can work with your copy of Synplify.

Most customers prefer Synplify because it works better on large designs and generally delivers better results.

But some customers prefer Yosys for smaller designs and because it can be used without a license server (especially for our customers who distribute our tools to their customers).

EFLX Compiler Evaluation

EFLX Compiler Evaluation

The EFLX Compiler is available for all of the process nodes we have completed GDS designs for: 40/28/22/16/12/7 nm.

We can enable you to evaluate our software at no cost so you can run your Verilog RTL designs on the compiler for the node you want to see density and performance for and process/voltage/temperature corner supported by the standard cell library.

Our Solutions Architecture team can work with you to give you a tutorial on the tools; show you how to run the numerous example designs we send with the compiler; and how to use the tools to complete your evaluation quickly.

Contact us at to request a software evaluation license for our EFLX Compiler.

Integrate our SW in your tool chain

Enable Your Customers to Program Your SoC

Many of our customers want to enable their customers to program the eFPGA in the SoC.

We are doing this now with Renesas’ ForgeFPGA for example where their GUI interface is built on top of our EFLX Compiler using Yosys for synthesis.

We can enable you in the same way with Yosys or Synplify.

Partionable FPGA allows you to give them libraries of subroutines that are pre-compiled so it’s easier for them to program. Or you can give them some modules like UARTs/SPIs and let them program other blocks without your code and theirs interacting.