How to design your eFPGA
Easily design the exact eFPGA you need with EFLX® compiler
Software is critical for an FPGA. The embedded FPGA is programmed using RTL or a netlist: Verilog or VHDL. This is mapped into the FPGA architecture using an industry standard synthesis tool then the EFLX Compiler which packs, places, routes, generates timing and generates the Configuration Bit Stream to be loaded into the EFLX array to implement the RTL function.
Contact us here to get an evaluation license for the process node you are interested in evaluating.
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Video Demonstration of EFLX Compiler
A ~10 minute demonstration of the key features of EFLX Compiler.
eFPGA Timing Signoff Methodology
Floor Planner allows a designer to quickly try out EFLX® arrays, using a specific IP core (EFLX4K shown here), with different sizes and combinations of Logic/DSP.
There are two types of EFLX cores: all-Logic (called “LM” in the floor planner) and DSP, were ~1/4 of the logic is replaced with strips of MACs with 22×22 multipliers, 48-bit pre-adder and 48-bit accumulator. The MACs are pipelined in strips of 10: the pipelining is directly between MACs without using the interconnect network for even higher performance and density.
More information on the structure and pipelining of DSP MACs is available HERE.
In the floor planner, first the user moves the arrow in the upper right corner to set the array dimension. The grid shown is 8×8 – we have already fabricated a 7×7 array. Array sizes can be square, 1×1, 2×2, 3×3, … but can also be rectangular. Array sizes of up to 500K LUTs are supported now and soon will be >2M LUTs.
Once the user selects the array size, then they select the core type for each block in the array. The user can quickly and interactively try different array sizes and placements of DSP/Logic blocks to determine which gives the best density and speed for their requirements.
Once the user is happy with the array size/feature configuration, a tcl script generates the GDS of the desired array automatically from the floor planner, a .LEF and .LIB file, with all interface timing including the clock network and it’s connection to the rest of the SoC, is generated for the specific array instance. All of this takes a few hours to a few days, depending on array size/configuraiton.
Since we can quickly implement different array sizes and configurations, we encourage users to have multiple, different arrays in a single design if that gives them the best result. And if late in the process, the user changes their mind, we can easily give them larger or smaller arrays as needed.
Here is an example of a 7×7 floor plan, identical to the one used in our TSMC16FFC EFLX200K validation chip:
Once an array is defined, RTL/Verilog can be mapped to the array. The Placement Viewer shows the physical design by IP core and by RBB block within the core (color coding: green is MAC, magenta is RBB-M, gray is RBB-L; a pale color is an empty logic block).
This screen (above) examines the input and output connections of a given block in the design.
This screen (above) shows the block by block path from start to finish of a specific timing path (a timing path is the output of a flop to the input of another flop that goes through multiple logic stages).
Timing is computed based on outputs from Tempus/PrimeTime which describe every timing path through the EFLX array. Timing is available for each process node and for multiple corners for each process node.
Contact us HERE for a demo and for a software evaluation license to try on your FPGA ready RTL.
This screen shows the 7 corners available for the TSMC 16FFC process. An EDIF netlist can be selected and a corner can be selected for optimizing place & route. Timing corners are available for all of the nominal voltages that TSMC supports: currently the 0.8V Tj nominal corners are populated (+/- 10%) and 1V corners for closing hold times. In the example below, an 8K LUT design will be placed and routed with timing optimized for SS, 0.72V and 125C.
After place and route, a timing histogram is generated showing the number of critical paths at each speed. The worst case performance for this example is 510.5MHz or 1959ps. In the GUI, using the cursor, the rightmost histogram bar was selected (1900-2000ps): the pop-up window shows there are two paths in this histogram.
Then, in this example, the 1959ps path is selected in the first pop-up window, which generates a 2nd pop-up window (see below) showing the 5% slowest paths in the logic cone of this path. Using this, a designer can see if one particular path is much longer and consider options to improve it.
Then, drilling down further, the designer can look at any of the paths in the logic cone (in the example below the 1946ps path is selected in the middle pop-up box). Once a path is selected, the designer can see every stage from the output of one flip flop through the various logic and net delays that make up the total path delay.
These data are based on silicon-sign-off data from Cadence Tempus, using TSMC/GF cell libraries (CCS), wire load models (QRC), in the TSMC/GF sign-off corners (e.g. SSGNP 0.72V, -40C RCworst-Cworst-T, AOCV) following TSMC timing sign-off guidelines. The database of timing reports and SDF timing annotation is then parsed by the EFLX Compiler to perform timing-analysis on your design in each corner. This rigorous ASIC timing signoff method ensures your RTL running on the EFLX array will meet the EFLX Compiler timing the same way you designed your ASIC to meeting timing under worst-case conditions. Unlike other FPGA companies, no timing margins or derates needs to be added to our timing-analysis reports because we use the same methodology you do for the rest of your chip.